The present invention relates to a semiconductor memory device, a method of fabricating the same, and devices employing the semiconductor memory device.
Non-volatile memory devices retain stored information even when not powered. One example of a non-volatile memory device is a flash memory. Many non-volatile memories have a memory cell array structure where the memory cells are floating gate transistors. Generally, these memory cells include a floating gate disposed between a semiconductor substrate and a control gate. A tunnel insulation layer often separates the floating gate from the semiconductor substrate. A drain and source are generally disposed on either side of the floating gate in the semiconductor substrate. During operation, charges are injected into or pulled from the floating gate by application of voltages to the control gate, drain and/or source.
A potential Vfg of the floating gate when a write potential Vcg is applied to the control gate is determined by capacitive coupling as represented by equations 1 and 2 below:Vfg=Cr(Vcg−Vt−Vt0)  (1)Cr=Cip/(Cip+Ctun)  (2)where Vt is the present cell transistor threshold value, Vt0 is the threshold value (neutral threshold value) when no electric charge is stored in the floating gate, and Cr is the capacitive coupling ratio of the memory cell. As shown by equation 2, the capacitive coupling ratio Cr depends on i) the capacitance Cip between the control gate and the floating gate and ii) the capacitance Ctun between the floating gate and the semiconductor substrate.
As Vfg rises, an electric field acting on the tunnel insulation layer increases, and this facilitates injection of electric charge into the floating gate. In addition, according to the above equations, when Vcg is constant, Vfg increases in proportion to a capacitance ratio Cr. That is, when this capacitance ratio Cr is large, a Vfg large enough to move electric charge can be obtained even if the write potential Vcg is decreased. As a consequence, the write potential can be reduced.